WDT_MODE1=NOTHING, WDT_MODE2=NOTHING, WDT_MODE0=NOTHING
Multi-Counter Watchdog Counter Configuration
| WDT_MODE0 | Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR0=WDT_MATCH0). 0 (NOTHING): Do nothing 1 (INT): Assert WDT_INTx 2 (RESET): Assert WDT Reset 3 (INT_THEN_RESET): Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt |
| WDT_CLEAR0 | Clear Watchdog Counter when WDT_CTR0=WDT_MATCH0. In other words WDT_CTR0 divides LFCLK by (WDT_MATCH0+1). 0: Free running counter 1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH0 is 1. |
| WDT_CASCADE0_1 | Cascade Watchdog Counters 0,1. Counter 1 increments the cycle after WDT_CTR0=WDT_MATCH0. 0: Independent counters 1: Cascaded counters |
| WDT_MODE1 | Watchdog Counter Action on Match. Action is taken on the next increment after the values match (WDT_CTR1=WDT_MATCH1). 0 (NOTHING): Do nothing 1 (INT): Assert WDT_INTx 2 (RESET): Assert WDT Reset 3 (INT_THEN_RESET): Assert WDT_INTx, assert WDT Reset after 3rd unhandled interrupt |
| WDT_CLEAR1 | Clear Watchdog Counter when WDT_CTR1==WDT_MATCH1. In other words WDT_CTR1 divides LFCLK by (WDT_MATCH1+1). 0: Free running counter 1: Clear on match. In this mode, the minimum legal setting of WDT_MATCH1 is 1. |
| WDT_CASCADE1_2 | Cascade Watchdog Counters 1,2. Counter 2 increments the cycle after WDT_CTR1=WDT_MATCH1. It is allowed to cascade all three WDT counters. 0: Independent counters 1: Cascaded counters. When cascading all three counters, WDT_CLEAR1 must be 1. |
| WDT_MODE2 | Watchdog Counter 2 Mode. 0 (NOTHING): Free running counter with no interrupt requests 1 (INT): Free running counter with interrupt request that occurs one LFCLK cycle after the specified bit in CTR2 toggles (see WDT_BITS2). |
| WDT_BITS2 | Bit to observe for WDT_INT2: 0: Assert after bit0 of WDT_CTR2 toggles (one int every tick) … 31: Assert after bit31 of WDT_CTR2 toggles (one int every 2^31 ticks) |